FIG. 8 is a view showing a known phase shift circuit (published in Technical Report of IEICE, MW 2001-27, pp. 15–22, June 2001).
In FIG. 8, 2 designates a high frequency signal input/output terminal, 6a a first field-effect transistor (hereinafter referred to as FET), 6b a second FET, 9 a bias terminal for the first FET and the second FET, 10 a capacitor, 11 an inductor, and 12 ground.
The capacitor 10 has one terminal connected with a drain electrode (or source electrode) of the FET 6b, and the other terminal connected with a high frequency signal input/output terminal 2, and the FET 6b also has a source electrode (or drain electrode) grounded. The inductor 11 has one terminal connected with a drain electrode (or source electrode) of the FET 6a, and the other terminal connected with the high frequency signal input/output terminal 2, and the FET 6a also has a source electrode (or drain electrode) grounded. Here, note that a series circuit comprising the FET 6a and the inductor 11 is connected in parallel with a series circuit comprising the FET 6b and the capacitor 10.
In addition, the FET 6a and the FET 6b act as switches for switching between an on-state and an off-state. The bias terminal 9 is connected with gate electrodes of the FET 6a and the FET 6b, respectively, so that the FET 6a and the FET 6b are driven to operate by the same bias voltage.
When a gate voltage of the same potential as those of a drain voltage and a source voltage of the FET 6a is applied to the bias terminal 9, the FET 6a is turned into an on-state, exhibiting resistivity (hereinafter referred to as on-resistance). On the other hand, when a gate voltage equal to or below a pinch-off voltage is applied to the bias terminal 9, the FET 6a is turned into an off-state, exhibiting capacitivity (hereinafter referred to as off-capacitance). The FET 6b operates similarly.
Next, the operation of the known phase shift circuit of the above-mentioned configuration will be explained.
FIG. 9 shows an equivalent circuit diagram when the FET 6a and the FET 6b are both turned into on-states. 13a designates an on-resistance of the FET 6a, and 13b an on-resistance of the FET 6b. Assuming that the on-resistance 13a and the on-resistance 13b are small enough, the circuit shown in FIG. 9 can be considered as a parallel LC circuit comprising the inductor 11 and the capacitor 10. Thus, a signal input from the high frequency signal input/output terminal 2 is reflected due to a phase rotation generated by the above-mentioned parallel LC circuit, so that it is output from the high frequency signal input/output terminal 2.
FIG. 10 shows an equivalent circuit diagram when the FET 6a and the FET 6b are both turned into off states. 14a designates an off-capacitance of the FET 6a, and 14b an off-capacitance of the FET 6b. Assuming that an admittance presented by the series circuit comprising the capacitor 10 and the off-capacitance 14b is small enough, the circuit shown in FIG. 10 can be considered as a series LC circuit comprising the inductor 11 and the off-capacitance 14a. Thus, a signal input from the high frequency signal input/output terminal 2 is reflected due to a phase rotation generated by the above-mentioned series LC circuit, so that it is output from the high frequency signal input/output terminal 2.
The difference between the reflected phase generated by the above-mentioned parallel LC circuit and the reflected phase generated by the above-mentioned series LC circuit is assumed to be a required amount of phase shift. With such an assumption, by switching the on/off states of the FET 6a and the FET 6b, the signal input from the high frequency signal input/output terminal 2 is reflected while obtaining a desired amount of phase shift, and it is then output from the high frequency signal input/output terminal 2.
As described above, the known phase shift circuit is configured such that it requires two switching elements, and hence there has been a problem that the circuit is enlarged in size.
The present invention is intended to solve the problem as referred to above, and has for its object to provide a phase shift circuit and a phase shifter which are small in size and wide in bandwidth.